Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
Electronic Design

CMOS Circuit Design, Layout, and Simulation, Second Edition

CMOS technology has dominated the IC business for the last 25 years and will continue to do so for another 25 years, according to the author of CMOS Circuit Design, Layout, and Simulation. He explains ...
EDN

IC Performance: Challenges in Layout with CMOS Technology Nodes

Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying ...
TechRepublic

CMOS Circuit Layout Design for Sub Threshold Leakage Power Optimization

The recent reduction in transistor size using scaling will cause sub-threshold leakage currents to become an increasingly large component of total power dissipation. In this paper, a stack transistor ...
EDN

Additional structures in analog layout beyond schematic

A schematic diagram is not a detailed blueprint of an analog circuit; instead, it’s more like architectural sketch of the circuit. Look at any schematic for a CMOS analog IC circuit and you will see ...