Semiconductor Engineering

Aren’t We Beyond That?

The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
Electronic Design

Extending Formal Verification Methodologies Beyond The Gate Level

In recent years, formal verification has become the verification methodology of choice for many designers and verification engineers. It's now in the mainstream marketplace, as it's easy to use, ...