The ADF41020 PLL frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up-conversion and down-conversion sections of wireless receivers and transmitters. Its high ...
The AD9577 provides a multioutput clock generator function along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on ...
With operation from 1800 MHz to 1860 MHz, the CPLL58-1800-1860 phase-locked loop (PLL)/synthesizer offers a typical step size of 10 kHz. The unit, which comes in a 0.582-in. x 0.8-in. 0.15-in. SMD ...
Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
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