Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
EDN

Getting started in structured assembly in complex SoC designs

The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer ...
Semiconductor Engineering

Streamlining SoC Design With Advanced IP And Integration Solutions

As system-on-chip (SoC) complexity grows, so does the necessity for products that seamlessly connect IP and streamline integration processes, minimize manual errors, and enhance productivity. The ...
Nasdaq

Synopsys Launches the Era of Smarter SoC Design with ML-Driven Big Data Analytics Technology

Synopsys DesignDash Autonomously Uncovers Untapped, Actionable Design Insights to Accelerate the IC Design Process The digital design flow holds a wealth of information from myriad sources that, ...
EDN

Automated tool suite speeds SoC design

You can spend a month hand-crafting the last few hundred square microns of silicon out of a SoC (System-on-Chip) design, or you can put your product on the market one month quicker. Forget the ...
Nasdaq

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

Next-generation CXL VIP and System VIP tools provide faster path to testing and compliance with the latest standard SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) ...
Design And Reuse

Indian Chip Design Services Provider Mirafra Tapes Out 22-nm SoC

Mirafra Technologies, a Bengaluru, India-based semiconductor design services company, has developed and taped out a 22-nm SoC called Ramanujan. The project is part of an internal effort to provide ...
Forbes

Cadence Brings Big Data And AI Analytics To SoC Verification

Forbes contributors publish independent expert analyses and insights. I write about disruptive companies, technologies and usage models. Over the years, the cost of designing a system on chip (SoC) ...
Business Wire

SiFive and Synopsys Collaborate to Accelerate SoC Design

SANTA CLARA, Calif. & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--SiFive and Synopsys, Inc. (Nasdaq: SNPS) today announced their new collaboration to accelerate the design and verification of SiFive ...
Seeking Alpha

Synopsys and TSMC Collaborate to Accelerate 2nm Innovation for Advanced SoC Design with Certified Digital and Analog Design Flows

Design Flow Achieved Multiple Successful Test Chip Tape-Outs on TSMC N2 Process; Broad IP Portfolio in Development to Speed Time to Market Highlights: Synopsys' (SNPS) certified digital and analog ...
Electronic Design

Manage ASIC, SoC Design Risk with Leading-Edge Verification Services

Value in design prototyping using FPGAs. Validating the design with firmware. How the process works. Identifying companies with the right experience and expertise in FPGA and design prototyping ...
Electronic Design

Designing Beyond The SoC

Flexible SoC systems, including external "hard" components, can be plugged together using FPGA-based Wishbone bus architecture cares that act as versatile interfacing layers. By Rob Evans Indeed, ...