EDN

Indian researchers propose new SoC test method

BANGALORE, India — With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test ...
EDN

3-D bin packing algorithm proposed for SoC testing

Researchers from Mentor Graphics Corp. are proposing a more complete way to test multiple cores on a system-on-chip. At the International Test Conference, Mentor presented a paper that defines SoC ...
Electronic Design

Synopsys Debuts DesignWare STAR Hierarchical System to Accelerate SoC Test

September 11, 2013. Synopsys Inc. has announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ...
Electronic Design

Tackling Next-Generation RF SOC Test

Developing an automated production test solution for current and next-generation complex RF SIP/SOC devices is an increasingly difficult task. Both the test program and the device interface board (DIB ...