EDN

Using SystemVerilog for functional verification

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...
Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

Download this article in PDF format. The Portable Stimulus Specification (PSS) is all about reusing commonly used test atoms to create new scenarios more quickly. It saves us from wasting precious ...
Semiconductor Engineering

Commoditizing Constraints

Can a vendor differentiate itself by the quality of its constraint solver? The answer may be different between SystemVerilog and Portable Stimulus. Preparing articles for Semiconductor Engineering ...
Design-Reuse

System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study

This document discusses Random constraint-based verification and explains how random verification can complement the directed verification for the generic designs. In our case this is demonstrated by ...
Semiconductor Engineering

Making Declarative Modeling Modular: Portable Stimulus Introduces Dynamic Constraints

Naturally, Accellera’s Portable Stimulus Standard (PSS) supports the powerful capabilities of advanced verification techniques that are well-known in the industry today, including object-oriented ...
EDN

New simulation capabilities advance SystemVerilog

Santa Cruz, Calif. — Two verification providers — Mentor Graphics Corp. and Axiom Design Automation — are claiming new simulation technology this week that offers broad support for the emerging ...