Hackaday

FPGA Used VHDL For Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You ...
Hackaday

Did You Know YoSys Knows VHDL Too?

We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write in ...
Electronic Design

VHDL Code Offloads LED Blinking Task To A CPLD

An earlier Idea For Design (Hardware-Based LED Blinking Control Eliminates Software Overhead) described a very interesting way to offload the software overhead required for a microcontroller to drive ...
EDN

4-bit ALU using VHDL

The project is a 4-bit ALU in VHDL with a total of 16 operations which includes various arithmetic, logical and data calculations performed by coding the ALU in VHDL code. The project is a 4-bit ALU ...
EDN

FPGA design tool bypasses VHDL coding

CoDeveloper, a C language design tool for Altera Nios-based and Xilinx MicroBlaze-based programmable platforms, allows creation of a complete hardware/software application with no need to write VHDL ...
Design-Reuse

Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC

SystemC has gained wide acceptance in the design of new digital IPs. However, there are numerous IPs already designed in VHDL. With the advances in SystemC ecosystem, like IEEE standardization, TLM-2 ...