A significant paradigm shift in design methodology is taking place with RTL design handoff. Shrinking process nodes, increasing SoC design complexities, and tightened purse strings have made the ...
The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...
If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz.
The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level ...
Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...
MILPITAS, Calif., Oct. 27, 2010--Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, announced today that it has opened an office in the Research Triangle Park (RTP), ...
Rising design complexity causes innumerable headaches in achieving functional design closure. Startup firm Blue Pearl Software plans to address design closure at RTL using a combination of design-rule ...
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